Power-Efficient Transposed FIR Filter Architecture with Clock Gating for Real-Time Image Processing on FPGA. Conference Proceedings in Science and Management, [S. l.], v. 1, n. 2, p. 29–33, 2026. DOI: 10.68337/cpsm.v1.i2.2026-029. Disponível em: https://cpsmse.com/index.php/cpsm/article/view/40. Acesso em: 31 oct. 2026.