Power-Efficient Transposed FIR Filter Architecture with Clock Gating for Real-Time Image Processing on FPGA
DOI:
https://doi.org/10.68337/cpsm.v1.i2.2026-029Keywords:
Transposed FIR architecture, FPGA implementation, image processing, image denoising, noise reduction, real-time image processing, HDL design, low-pass filtering, hardware optimization, high-speed DSPAbstract
Finite impulse response (FIR) filters are widely used in digital image processing because of their stability, linear phase response, and ease of implementation. This paper proposes a low-power transposed FIR filter structure with clock gating for real-time image processing on field-programmable gate arrays (FPGAs). The transposed architecture supports parallel multiply-accumulate processing, shortens the critical path, and allows pipelining for high-throughput operation, while clock gating limits switching activity to save energy. The N-tap FIR filter was designed with multipliers, adders, and unit delay elements in a hardware description language and synthesized on an FPGA. The design reduced delay by 4.95% and total on-chip power by 87.02%, with dynamic and static power reduced by 87.74% and 35.85%, respectively. Signal, logic, and input/output (I/O) power also fell, the junction temperature decreased, and the thermal margin increased, which improves reliability. Look-up table (LUT) usage rose by only 0.21%, so the design offers a good balance among area, speed, and power and is suitable for real-time image processing on FPGA.
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